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CYDC128B16 1.8 v 4 k/8 k/16 k 16 and 8 k/16 k 8 consumobl dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 408-943-2600 document #: 001-01638 rev. *h revised march 1, 2011 features true dual-ported memory cells which allow simultaneous access of the same memory location 4/8/16 k 16 and 8/16 k 8 organization high speed access: 40 ns ultra low operating power ? active: i cc = 15 ma (typical) at 55 ns ? active: i cc = 25 ma (typical) at 40 ns ? standby: i sb3 = 2 a (typical) port-independent 1.8 v, 2.5 v, and 3.0 v i/os pb-free 14 14 1.4 mm 100-pin thin quad flat pack (tqfp) package full asynchronous operation pin select for master or slave expandable data bus to 32 bits with master/slave chip select when using more than one device on-chip arbitration logic on-chip semaphore logic input read registers (irr) and output drive registers (odr) int flag for port-to- port communication separate upper byte and lower byte control commercial and industrial temperature ranges selection guide for v cc = 1.8 v description CYDC128B16 ?40 CYDC128B16 ?55 unit port i/o voltages (p1-p2) 1.8 v-1.8 v 1.8 v-1.8 v maximum access time 40 55 ns typical operating current 25 15 ma typical standby current for i sb1 22 a typical standby current for i sb3 22 a selection guide for v cc = 2.5 v description CYDC128B16 ?40 CYDC128B16 ?55 unit port i/o voltages (p1-p2) 2.5 v-2.5 v 2.5 v-2.5 v maximum access time 40 55 ns typical operating current 39 28 ma typical standby current for i sb1 66 a typical standby current for i sb3 44 a selection guide for v cc = 3.0 v description CYDC128B16 ?40 CYDC128B16 ?55 unit port i/o voltages (p1-p2) 3.0 v-3.0 v 3.0 v-3.0 v maximum access time 40 55 ns typical operating current 49 42 ma typical standby current for i sb1 77 a typical standby current for i sb3 66 a [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 2 of 29 notes 1. a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k devices. 2. busy is an output in master mode and an input in slave mode. io control address decode mailboxes int l int r address decode 16k x 16 dual ported array io control interrupt arbitration semaphore a [13:0] r ce r busy r i/o[15:0] r lb r i/o[15:0] l lb l oe l busy l a[13:0] l r/w l ce l m/s ub l ub r sem l sem r input read register and output drive register ce r oe r oe r r/w r r/w r odr 0 - odr 4 ce l oe l r/w l irr 0 ,irr 1 sfen top level block diagram [1, 2] [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 3 of 29 contents features ...............................................................................1 selection guide for v cc = 1.8 v .........................................1 selection guide for vcc = 2.5 v ........................................1 selection guide for vcc = 3.0 v 1 top level block diagram....................................................2 pin configurations .............................................................4 pin definitions ....................................................................5 functional description .......................................................6 power supply ................................................................6 write operation .............................................................6 read operation .............................................................6 interrupts .......................................................................6 busy ..............................................................................6 master/slave .................................................................6 input read register ......................................................7 output drive register ....................................................7 semaphore operation . .............. .............. .............. ........7 architecture ........................................................................8 maximum ratings .............................................................10 operating range ...............................................................10 electrical characteristics for vcc = 1.8 v over the operating range ...............................................10 electrical characteristics for vcc = 2.5 v over the operating range ...............................................12 electrical characteristics for 3.0 v over the operating range ...............................................13 capacitance ......................................................................13 switching characteristics for vcc = 1.8v ......................14 switching characteristics for vcc = 2.5 v over the operating range .................................................16 switching characteristics for vcc = 3.0 v over the operating range .................................................17 switching waveforms ......................................................19 ce l valid first .............................................................23 left address valid first ........ ......................................23 ordering information ........................................................25 8k x16 1.8v asynchronous du al-port sram ......... .....25 ordering code defintions ...... ......................................25 package diagram ..............................................................26 acronyms ..........................................................................27 document history page .......... .........................................28 sales, solutions, and legal information ........................29 worldwide sales and design supp ort ............ .............29 products ......................................................................29 psoc solutions ...........................................................29 [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 4 of 29 pin configurations figure 1. 100-pin tqfp (top view) [3] notes 3. leave this pin unconnected. no trace or power component can be connected to this pin. 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a 4r a 5r a 6r a 7r a 8r ce r a 10r int r a 9r v cc a 11r nc [7] v ddior busy r sem r a 12r [3] irr1 [6] i/o 15r i/o 14r i/o 13r v ss i/o 12r i/o 11r i/o 10r v ss 58 57 56 55 54 53 52 51 a 4l a 5l a 6l a 7l a 8l ce l a 10l int l a 9l v cc a 11l m/s v ddiol busy l sem l a 12l [3] irr0 [5] i/o 0l i/o 1l i/o 2l v ss i/o 3l i/o 4l i/o 5l v ss 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a 3l a 2l a 1l a 0l ub l lb l odr0 r/w l v ss v ss odr2 v ss r/w r sfen oe l odr3 odr4 oe r lb r ub r a 0r a 1r a 2r a 3r odr1 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/o 9r i/o 8r v ddior i/o 7r i/o 6r i/o 5r i/o 1r i/o 4r i/o 2r nc [7] i/o 15l i/o 12l i/o 11l i/o 3r v ss i/o 14l i/o 13l v ss i/o 10l i/o 9l i/o 8l v ddiol i/o 7l i/o 6l i/o 0r 33 32 31 30 29 28 27 26 CYDC128B16 [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 5 of 29 pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 13l a 0r ?a 13r address (a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k devices). i/o 0l ?i/o 15l i/o 0r ?i/o 15r data bus input/output for x16 devices; i/o 0 ?i/o 7 for x8 devices. sem l sem r semaphore enable ub l ub r upper byte select (i/o 8 ?i/o 15 for x16 devices; not applicable for x8 devices). lb l lb r lower byte select (i/o 0 ?i/o 7 for x16 devices; not applicable for x8 devices). int l int r interrupt flag busy l busy r busy flag irr0, irr1 input read register (irr) for CYDC128B16. odr0-odr4 output drive register; these outputs are open drain. sfen special function enable m/s master or slave select v cc core power gnd ground v ddiol left port i/o voltage v ddior right port i/o voltage nc no connect. leave this pin unconnected. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 6 of 29 functional description the CYDC128B16 is a low power complementary metal oxide semiconductor (cmos) 4k, 8k,16k x 16, and 8/16k x 8 dual-port static ram. arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be used as standalone 16-bit dual-port static rams or multiple devices can be combined in order to function as a 32-bit or wider ma ster/slave dual-port static ram. an m/s pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semap hore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip enable (ce ) pin. the CYDC128B16 are available in 100-pin tqfp packages. power supply the core voltage (v cc ) can be 1.8 v, 2.5 v or 3.0 v, as long as it is lower than or equal to the i/o voltage. each port can operate on independent i/o voltages. this is determined by what is connected to the v ddiol and v ddior pins. the supported i/o standards are 1.8-v/2.5-v lvcmos and 3.0-v lvttl. write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the r/w pin (see figure 6 on page 20) or the ce pin (see figure 7 on page 20). required inputs for non-contention operations are summarized in table 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the us er must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (1fff for the CYDC128B16) is the mailbox for the right port and the second highest memory location (1ffe for the CYDC128B16) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user-defined. each port can read the other port?s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. on power up, an initialization program should be run and the interrupts for both ports must be read to reset them. the operation of the interrupts and their interaction with busy are summarized in table 2 . busy the CYDC128B16 provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predictable which port gets that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle durin g a contention si tuation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 7 of 29 input read register the input read register (irr) captures the status of two external input devices that are connected to the input read pins. the contents of the irr read from address x0000 from either port. during reads from the irr, dq0 and dq1 are valid bits and dq<15:2> are don?t care. writes to address x0000 are not allowed from either port. address x0000 is not available for standard memory accesses when sfen = v il . when sfen = v ih , address x0000 is available for memory accesses. the inputs will be 1.8-v/2.5-v lvcmos or 3.0-v lvttl, depending on the core voltage supply (v cc ). refer to table 3 for input read register operation. output drive register the output drive register (odr) determines the state of up to five external binary state devices by providing a path to v ss for the external circuit. these outputs are open drain. the five external devices can operate at different voltages (1.5 v v ddio 3.5 v) but the combined current cannot exceed 40 ma (8 ma max for each external device). the status of the odr bits are set using standard write accesses from either port to address x0001 with a ?1? corresponding to on and ?0? corre- sponding to off. the status of the odr bits c an be read with a standard read access to address x0001. when sfen = v il , the odr is active and address x0001 is not available for memory accesses. when sfen = v ih , the odr is inactive and address x0001 can be used for standard accesses. during reads and writes to odr dq<4:0> are valid and dq<15:5> are don?t care. refer to table 4 for output drive register operation. semaphore operation the CYDC128B16 provides eight semaphore latches that are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assume s the right port has control and continues to poll the semaphore. when the right side has relin- quished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 5 shows sample semaphore opera- tions. when reading a semaphore, all 16/8 data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side controls the semaphore. on power up, both ports should write ?1? to all eight semaphores. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 8 of 29 architecture the CYDC128B16 consists of an array of 4k, 8k, or 16k words of 16 dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the device can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the device also has an automatic power down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. table 1. non-contending read/write inputs outputs [1] operation ce r/w oe ub lb sem i/o 8 ? i/o 15 i/o 0 ? i/o 7 h x x x x h high z high z deselected: power down x x x h h h high z high z deselected: power down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag lxxlxl not allowed l x x x l l not allowed 1. this column applies to x16 devices only. table 2. interrupt operation example (assumes busy l = busy r = high) [1] function left port right port r/w l ce l oe l a 0l?13l int l r/w r ce r oe r a 0r?13r int r set right int r flag l l x 3fff [2] xxxx x l [3] reset right int r flagxxxxxxll3fff [2] h [4] set left int l flag x x x x l [4] llx 3ffe [2] x reset left int l flag x l l 3ffe [2] h [3] xxx x x 1. see interrupts functional description for sp ecific highest memory locations by device. 2. see functional description for specific addresses by device. 3. if busy l = l, then no change. 4. if busy r = l, then no change. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 9 of 29 table 3. input read register operation [1, 2] sfen ce r/w oe ub lb addr i/o 0 ? i/o 1 i/o 2 ? i/o 15 mode hlhlllx0000-maxvalid [3] valid [3] standard memory access l l h l x l x0000 valid [4] x irr read 1. sfen = v il for irr reads. 2. sfen active when either ce l = v il or ce r = v il . it is inactive when ce l = ce r = v ih . 3. ub or lb = v il . if lb = v il , then dq<7:0> are valid. if ub = v il then dq<15:8> are valid. 4. lb must be active (lb = v il ) for these bits to be valid. table 4. output drive register [ 1 ] sfen ce r/w oe ub lb addr i/o 0 ? i/o 4 i/o 5 ? i/o 15 mode hlhx [2] l [3] l [3] x0000-max valid [3] valid [3] standard memory access lllxxlx0001valid [4] x odr write [1, 3] llhlxlx0001valid [4] x odr read [1] 1. sfen = v il for odr reads and writes. 2. output enable must be low (oe = v il ) during reads for valid data to be output. 3. during odr writes data will also be written to the memory. table 5. semaphore operation example function i/o 0 ? i/o 15 left i/o 0 ? i/o 15 right status no action 1 1 semaphore-free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore-free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore-free [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 10 of 29 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. [4] storage temperature .. ............... .............. ... ?65c to +150c ambient temperature with power applied ............. ............... .............. ... ?55c to +125c supply voltage to ground potenti al ...............?0.5 v to +3.3 v dc voltage applied to outputs in high-z state ........................ ?0.5 v to v cc + 0.5 v dc input voltage [5] ............................... ?0.5 v to v cc + 0.5 v output current into outputs (low) .............................. 90 ma static discharge voltage.......................................... > 2000 v latch up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 1.8 v 100 mv 2.5 v 100 mv 3.0 v 300 mv industrial ?40c to +85c 1.8 v 100 mv 2.5 v 100 mv 3.0 v 300 mv electrical characteristics for v cc = 1.8 v over the operating range parameter description CYDC128B16 CYDC128B16 unit -40 -55 p1 i/o voltage p2 i/o voltage min typ max min typ max v oh output high voltage (i oh = ?100 a) 1.8 v (any port) v ddio ? 0.2 v ddio ? 0.2 v output high voltage (i oh = ?2 ma) 2.5 v (any port) 2.0 2.0 v output high voltage (i oh = ?2 ma) 3.0 v (any port) 2.1 2.1 v v ol output low voltage (i ol = 100 a ) 1.8 v (any port) 0.2 0.2 v output high voltage (i ol = 2 ma) 2.5 v (any port) 0.4 0.4 v output high voltage (i ol = 2 ma) 3.0 v (any port) 0.4 0.4 v v ol odr odr output low voltage| (i ol = 8 ma ) 1.8 v (any port) 0.2 0.2 v 2.5 v (any port) 0.2 0.2 v 3.0 v (any port) 0.2 0.2 v v ih input high voltage 1.8 v (any port) 1.2 v ddio + 0.2 1.2 v ddio + 0.2 v 2.5 v (any port) 1.7 v ddio + 0.3 1.7 v ddio + 0.3 v 3.0 v (any port) 2.0 v ddio + 0.2 2.0 v ddio + 0.2 v v il input low voltage 1.8 v (any port) ?0.2 0.4 ?0.2 0.4 v 2.5 v (any port) ?0.3 0.6 ?0.3 0.6 v 3.0 v (any port) ?0.2 0.7 ?0.2 0.7 v i oz output leakage current 1.8 v 1.8 v ?1 1 ?1 1 a 2.5 v 2.5 v ?1 1 ?1 1 a 3.0 v 3.0 v ?1 1 ?1 1 a i cex odr odr output leakage current. v out =v ddio 1.8 v 1.8 v ?1 1 ?1 1 a 2.5 v 2.5 v ?1 1 ?1 1 a 3.0 v 3.0 v ?1 1 ?1 1 a notes 4. the voltage on any input or i/o pin can not exceed the power pin during power-up. 5. pulse width < 20 ns. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 11 of 29 i ix input leakage current 1.8 v 1.8 v ?1 1 ?1 1 a 2.5 v 2.5 v ?1 1 ?1 1 a 3.0 v 3.0 v ?1 1 ?1 1 a i cc operating current (v cc = max, i out =0 ma) outputs disabled industrial 1.8 v 1.8 v 25 40 15 25 ma i sb1 standby current (both ports ttl level) ce l and ce r v cc ? 0.2, sem l = sem r = v cc ? 0.2, f = f max industrial 1.8 v 1.8 v 2 6 2 6 a i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max industrial 1.8 v 1.8 v 8.5 18 8.5 14 ma i sb3 standby current (both ports cmos level) ce l and ce r v cc ? 0.2v, sem l and sem r > v cc ? 0.2v, f = 0 industrial 1.8 v 1.8 v 2 6 2 6 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [1] industrial 1.8 v 1.8 v 8.5 18 8.5 14 ma 1. max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3. electrical characteristics for v cc = 1.8 v (continued) over the operating range parameter description CYDC128B16 CYDC128B16 unit -40 -55 p1 i/o voltage p2 i/o voltage min typ max min typ max [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 12 of 29 electrical characteristics for v cc = 2.5 v over the operating range parameter description CYDC128B16 CYDC128B16 unit -40 -55 p1 i/o voltage p2 i/o voltage min typ max min typ max v oh output high voltage (i oh = ?2 ma) 2.5 v (any port) 2.0 2.0 v output high voltage (i oh = ?2 ma) 3.0 v (any port) 2.1 2.1 v v ol output low voltage (i ol = 2 ma ) 2.5 v (any port) 0.4 0.4 v output low voltage (i ol = 2 ma ) 3.0 v (any port) 0.4 0.4 v v ol odr odr output low voltage (i ol = 8 ma ) 2.5 v (any port) 0.2 0.2 v 3.0 v (any port) 0.2 0.2 v v ih input high voltage 2.5 v (any port) 1.7 v ddio + 0.3 1.7 v ddio + 0.3 v 3.0 v (any port) 2.0 v ddio + 0.2 2.0 v ddio + 0.2 v v il input low voltage 2.5 v (any port) ?0.3 0.6 ?0.3 0.6 v 3.0 v (any port) ?0.2 0.7 ?0.2 0.7 v i oz output leakage current 2.5 v 2.5 v ?1 1 ?1 1 a 3.0 v 3.0 v ?1 1 ?1 1 a i cex odr odr output leakage current. v out =v cc 2.5 v 2.5 v ?1 1 ?1 1 a 3.0 v 3.0 v ?1 1 ?1 1 a i ix input leakage current 2.5 v 2.5 v ?1 1 ?1 1 a 3.0 v 3.0 v ?1 1 ?1 1 a i cc operating current (v cc = max, i out = 0 ma) outputs disabled industrial 2.5 v 2.5 v 39 55 28 40 ma i sb1 standby current (both ports ttl level) ce l and ce r v cc ? 0.2, sem l = sem r = v cc ? 0.2, f=f max industrial 2.5 v 2.5 v 6 8 6 8 a i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max industrial 2.5 v 2.5 v 21 30 18 25 ma i sb3 standby current (both ports cmos level) ce l and ce r v cc ? 0.2v, sem l and sem r > v cc ? 0.2v, f = 0 industrial 2.5 v 2.5 v 4 6 4 6 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [1] industrial 2.5 v 2.5 v 21 30 18 25 ma 1. max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 13 of 29 ] electrical characteristics for 3.0 v over the operating range parameter description CYDC128B16 CYDC128B16 unit -40 -55 p1 i/o voltage p2 i/o voltage min typ max min typ max v oh output high voltage (i oh = ?2 ma) 3.0 v (any port) 2.1 2.1 v v ol output low voltage (i ol = 2 ma) 3.0 v (any port) 0.4 0.4 v v ol odr odr output low voltage (i ol = 8 ma ) 3.0 v (any port) 0.2 0.2 v v ih input high voltage 3.0 v (any port) 2.0 v ddio + 0.2 2.0 v ddio + 0.2 v v il input low voltage 3.0 v (any port) ?0.2 0.7 ?0.2 0.7 v i oz output leakage current 3.0 v 3.0 v ?1 1 ?1 1 a i cex odr odr output leakage current. v out =v cc 3.0 v 3.0 v ?1 1 ?1 1 a i ix input leakage current 3.0v 3.0 v ?1 1 ?1 1 a i cc operating current (v cc = max, i out = 0 ma) outputs disabled industrial 3.0v 3.0 v 49 70 42 60 ma i sb1 standby current (both ports ttl level) ce l and ce r v cc ? 0.2, sem l = sem r = v cc ? 0.2, f = f max industrial 3.0 v 3.0 v 7 10 7 10 a i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max industrial 3.0 v 3.0 v 28 40 25 35 ma i sb3 standby current (both ports cmos level) ce l and ce r v cc ? 0.2v, sem l and sem r > v cc ? 0.2v, f = 0 industrial 3.0 v 3.0 v 6 8 6 8 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f= f max [1] industrial 3.0 v 3.0 v 28 40 25 35 ma 1. max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or c ontrol lines change. this applies only to inputs at cmos level standby i sb3. capacitance parameter [ 1 ] description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 3.0v 9pf c out output capacitance 10 pf 1. tested initially and after any design or proc ess changes that may affect these parameters. [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 14 of 29 7 figure 2. ac test loads and waveforms switching characteristics for v cc = 1.8v over the operating range [1] parameter description CYDC128B16 CYDC128B16 unit -40 -55 min max min max read cycle t rc read cycle time 40 55 ns t aa address to data valid 40 55 ns t oha output hold from address change 5 5 ns t ace [2] ce low to data valid 40 55 ns t doe oe low to data valid 25 30 ns t lzoe [3, 4, 5] oe low to low z 5 5 ns t hzoe [3, 4, 5] oe high to high z 15 25 ns t lzce [3, 4, 5] ce low to low z 5 5 ns t hzce [3, 4, 5] ce high to high z 15 25 ns t pu [5] ce low to power up 0 0 ns t pd [5] ce high to power down 40 55 ns t abe [2] byte enable access time 40 55 ns write cycle t wc write cycle time 40 55 ns t sce [2] ce low to write end 30 45 ns t aw address valid to write end 30 45 ns t ha address hold from write end 0 0 ns t sa [2] address setup to write start 0 0 ns t pwe write pulse width 25 40 ns t sd data setup to write end 20 30 ns t hd data hold from write end 0 0 ns t hzwe [4, 5] r/w low to high z 15 25 ns 1.8v gnd 90% 90% 10% 10% all input pulses (a) normal load (load 1) r1 3.0 v/2.5 v/1.8 v output r2 c = 30 pf v th = 0.8 v output (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 r2 3.0v/2.5v/1.8v output r th = 6 k 3 ns 3 ns including scope and jig) (used for t lz , t hz , t hzwe , and t lzwe 3.0v/2.5v 1.8v r1 1022 13500 r2 792 10800 c = 30 pf c = 5 pf [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 15 of 29 t lzwe [4, 5] r/w high to low z 0 0 ns t wdd [6] write pulse to data delay 55 80 ns t ddd [6] write data valid to read data valid 55 80 ns busy timing [ 7 ] t bla busy low from address match 30 45 ns t bha busy high from address mismatch 30 45 ns t blc busy low from ce low 30 45 ns t bhc busy high from ce high 30 45 ns t ps [8] port setup for priority 5 5 ns t wb r/w high after busy (slave) 0 0 ns t wh r/w high after busy high (slave) 20 35 ns t bdd [9] busy high to data valid 30 40 ns interrupt timing [7] t ins int set time 35 45 ns t inr int reset time 35 45 ns semaphore timing t sop sem flag update pulse (oe or sem )10 15 ns t swrd sem flag write to read time 10 10 ns t sps sem flag contention window 10 10 ns t saa sem address access time 40 55 ns 1. test conditions assume signal transition time of 3 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc , and output loading of the specified i oi /i oh and 30-pf load capacitance. 2. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 3. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 4. test conditions used are load 3. 5. this parameter is guaranteed but not tested. for information on port-to-port delay through ram cells from writing port to rea ding port, refer to read timing with busy waveform. 6. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wav eform. 7. test conditions used are load 2. 8. add 2ns to this value when the i/o ports are operating at different voltages. 9. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). switching characteristics for v cc = 1.8v over the operating range [1] (continued) parameter description CYDC128B16 CYDC128B16 unit -40 -55 min max min max [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 16 of 29 switching characteristics for v cc = 2.5 v over the operating range parameter description CYDC128B16 CYDC128B16 unit -40 -55 min max min max read cycle t rc read cycle time 40 55 ns t aa address to data valid 40 55 ns t oha output hold from address change 5 5 ns t ace [1] ce low to data valid 40 55 ns t doe oe low to data valid 25 30 ns t lzoe [2, 3, 4] oe low to low z 2 2 ns t hzoe [2, 3, 4] oe high to high z 15 15 ns t lzce [2, 3, 4] ce low to low z 2 2 ns t hzce [2, 3, 4] ce high to high z 15 15 ns t pu [4] ce low to power up 0 0 ns t pd [4] ce high to power down 40 55 ns t abe [1] byte enable access time 40 55 ns write cycle t wc write cycle time 40 55 ns t sce [1] ce low to write end 30 45 ns t aw address valid to write end 30 45 ns t ha address hold from write end 0 0 ns t sa [1] address setup to write start 0 0 ns t pwe write pulse width 25 40 ns t sd data setup to write end 20 30 ns t hd data hold from write end 0 0 ns t hzwe [3, 4] r/w low to high z 15 25 ns t lzwe [3, 4] r/w high to low z 0 0 ns t wdd [5] write pulse to data delay 55 80 ns t ddd [5] write data valid to read data valid 55 80 ns busy timing [6] t bla busy low from address match 30 45 ns t bha busy high from address mismatch 30 45 ns t blc busy low from ce low 30 45 ns t bhc busy high from ce high 30 45 ns t ps [7] port set up for priority 5 5 ns t wb r/w high after busy (slave) 0 0 ns t wh r/w high after busy high (slave) 20 35 ns t bdd [8] busy high to data valid 30 40 ns interrupt timing [6] t ins int set time 35 45 ns [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 17 of 29 t inr int reset time 35 45 ns semaphore timing t sop sem flag update pulse (oe or sem )10 15 ns t swrd sem flag write to read time 10 10 ns t sps sem flag contention window 10 10 ns t saa sem address access time 40 55 ns 1. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 2. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 3. test conditions used are load 3. 4. this parameter is guaranteed but not tested. for information on port-to-port delay through ram cells from writing port to rea ding port, refer to read timing with busy waveform. 5. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wav eform. 6. test conditions used are load 2. 7. add 2ns to this value when the i/o ports are operating at different voltages. 8. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). switching characteristics for v cc = 3.0 v over the operating range parameter description CYDC128B16 CYDC128B16 unit -40 -55 min max min max read cycle t rc read cycle time 40 55 ns t aa address to data valid 40 55 ns t oha output hold from address change 5 5 ns t ace [1] ce low to data valid 40 55 ns t doe oe low to data valid 25 30 ns t lzoe [2, 3, 4] oe low to low z 1 1 ns t hzoe [2, 3, 4] oe high to high z 15 15 ns t lzce [2, 3, 4] ce low to low z 1 1 ns t hzce [2, 3, 4] ce high to high z 15 15 ns t pu [4] ce low to power up 0 0 ns t pd [4] ce high to power down 40 55 ns t abe [1] byte enable access time 40 55 ns write cycle t wc write cycle time 40 55 ns t sce [1] ce low to write end 30 45 ns t aw address valid to write end 30 45 ns t ha address hold from write end 0 0 ns t sa [1] address setup to write start 0 0 ns t pwe write pulse width 25 40 ns t sd data setup to write end 20 30 ns switching characteristics for v cc = 2.5 v over the operating range (continued) parameter description CYDC128B16 CYDC128B16 unit -40 -55 min max min max [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 18 of 29 t hd data hold from write end 0 0 ns t hzwe [3, 4] r/w low to high z 15 25 ns t lzwe [3, 4] r/w high to low z 0 0 ns t wdd [5] write pulse to data delay 55 80 ns t ddd [5] write data valid to read data valid 55 80 ns busy timing [ 6 ] t bla busy low from address match 30 45 ns t bha busy high from address mismatch 30 45 ns t blc busy low from ce low 30 45 ns t bhc busy high from ce high 30 45 ns t ps [7] port set up for priority 5 5 ns t wb r/w high after busy (slave) 0 0 ns t wh r/w high after busy high (slave) 20 35 ns t bdd [8] busy high to data valid 30 40 ns interrupt timing [6] t ins int set time 35 45 ns t inr int reset time 35 45 ns semaphore timing t sop sem flag update pulse (oe or sem )10 15 ns t swrd sem flag write to read time 10 10 ns t sps sem flag contention window 10 10 ns t saa sem address access time 40 55 ns 1. to access ram, ce = l, ub = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 2. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe. 3. test conditions used are load 3. 4. this parameter is guaranteed but not tested. for information on port-to-port delay through ram cells from writing port to rea ding port, refer to read timing with busy waveform. 5. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wav eform. 6. test conditions used are load 2. 7. add 2ns to this value when the i/o ports are operating at different voltages. 8. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). switching characteristics for v cc = 3.0 v over the operating range (continued) parameter description CYDC128B16 CYDC128B16 unit -40 -55 min max min max [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 19 of 29 switching waveforms figure 3. read cycle no.1 (either port address access) [6, 7, 8] figure 4. read cycle no.2 (either port ce /oe access) [6, 9, 10] figure 5. read cycle no. 3 (either port) [6, 8, 11, 12] notes 6. r/w is high for read cycles. 7. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 8. oe = v il . 9. address valid prior to or coincident with ce transition low. 10. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . 11. r/w must be high during all address transitions. 12. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . t rc t aa t oha data valid previous data valid data out address t oha t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 20 of 29 figure 6. write cycle no.1: r/w controlled timing [11, 12, 13, 14, 15, 16] figure 7. write cycle no. 2: ce controlled timing [11, 12, 13, 18] notes 13. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 14. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 15. to access ram, ce = v il , sem = v ih . 16. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 17. transition is measured 0 mv from steady state with a 5-pf load (including scope and jig). this parameter is sampled and not 100% tested. 18. during this period, the i/o pins are in the out put state, and input signals must not be applied. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe [17] [17] [14] [15, 16] note 18 note 18 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa [15, 16] [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 21 of 29 figure 8. semaphore read af ter write timing, either side [19, 20] figure 9. timing diagra m of semaphore contention [21, 22] notes 19. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. 20. ce = high for the duration of the above timing (both write and read cycle). 21. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 22. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 data out valid match t sps match r/w l sem l r/w r sem r a 0l ?a 2l a 0r ?a 2r [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 22 of 29 figure 10. timing diagram of read with busy (m/s =high) [23] figure 11. write timing with busy input (m/s = low) note 23. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 23 of 29 figure 12. busy timing diagram no.1 (ce arbitration) figure 13. busy timing diagram no.2 (address arbitration) [24] note 24. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first [24] address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first left address valid first [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 24 of 29 figure 14. interrupt timing diagrams notes 25. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 26. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write 1fff (or 1/3fff) t wc right side clears int r : t ha read 1fff t rc t inr write 1ffe (or 1/3ffe) t wc right side sets int l : left side sets int r : left side clears int l : read 1ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (or 1/3fff) or 1/3ffe) [25] [26] [26] [26] [25] [26] [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 25 of 29 ordering information ordering code defintions 8k x16 1.8v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 55 CYDC128B16-55axi az0ab 100-pin pb-free tqfp industrial [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 26 of 29 package diagram figure 15. 100-pin thin plastic quad flat pack (tqfp) a100 51-85048 *e [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 27 of 29 acronyms acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output irr input read registers odr output drive registers oe output enable sem semaphore sram static random access memory tqdp thin quad flat pack we write enable [+] feedback
CYDC128B16 document #: 001-01638 rev. *h page 28 of 29 document history page document title: CYDC128B16 1.8 v 4 k/8 k/16 k 16 and 8 k/16 k 8 consumobl dual-port static ram document number: 001-01638 revision ecn submission date orig. of change description of change ** 385185 see ecn ydt new data sheet *a 396697 see ecn kgh updated isb2 and isb4 typo to ma. updated tins and tinr for -55 to 31ns. *b 404777 see ecn kgh updated i oh and i ol values for the 1.8v, 2.5v and 3.0v parameters v oh and v ol replaced -35 speed bin with -40 updated switching characteristics for v cc = 2.5v and v cc = 3.0v included note 34 *c 463014 see ecn hkh changed s pec title to from ?consumer dual -port? to ?consumobl dual-port? cypress internet release *d 505803 see ecn hkh corrected typo in feat ures and ordering info sections. cypress external web release. *e 735537 see ecn hkh corrected typo in pg5 power supply section updated tddd timing value to be consistent with twdd *f 2905507 04/06/2010 ydt removed parts cydc064b08-55axi, cydc064b16-55axi. updated package diagram. *g 2930445 05/11/2010 avf updated template. removed references to inactive parts from the data sheet. *h 3183900 02/28/11 esh added ordering code defintions [+] feedback
document #: 001-01638 rev. *h revised march 1, 2011 page 29 of 29 all products and company names mentioned in this document may be the trademarks of their respective holders. CYDC128B16 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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